1. Field of the Invention
The present invention relates to a charge storage capacitor and more particularly, to a charge storage capacitor including an encapsulation layer that can also function as a dielectric layer of the charge storage capacitor.
2. Discussion of the Related Art
Integrated circuit ferroelectric memory devices include an integrated circuit substrate which includes a cell region and a periphery region. A plurality of ferroelectric memory cells are formed in the cell region, including a plurality of ferroelectric capacitors. The ferroelectric capacitor in the ferroelectric memory cell includes a dielectric material that has a high dielectric constant and that can be polarized by an electric field, thus storing a memory data state. A polarization of the dielectric material remains until reversed by an opposite electrical field. This makes the dielectric memory cell non-volatile.
Conventionally, capacitors with a single ferroelectric layer, such as a PZT-F layer (ferroelectric layer formed of PZT (lead zirconate titanate)), are used for making both switchable ferroelectric capacitors (data storage capacitors) and charge pump capacitors or other charge storage capacitors. However, it is very difficult to optimize the ferroelectric properties of a ferroelectric layer, such as a PZT-F layer, for high permittivity capacitor applications such as charge pumps or other charge storage capacitors. Further, conventionally, an encapsulation layer, such as a PZT-E layer (encapsulation layer formed of PZT (lead zirconate titanate)) is utilized only for encapsulating and protecting the underlying ferroelectric capacitor including the PZT-F layer.
Accordingly, the present invention is directed to a charge storage capacitor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an improved charge storage capacitor.
Another object of the present invention is to provide a capacitor including a dielectric layer that is easy to optimize for both encapsulation and high permittivity dielectric properties.
Another object of the present invention is to provide a capacitor having a high charge storage capability that has low leakage current and relatively linear capacitance dependence on voltage.
Another object of the present invention is to provide an integrated circuit, including an improved charge storage and a ferroelectric memory cell, having a simple manufacture process.
Additional features and advantages of the invention will be set forth in the description, which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer.
In another aspect of the present invention, an integrated circuit including a capacitor includes a bottom, a first dielectric layer formed on the bottom electrode, a top electrode formed on the first dielectric layer, a second dielectric layer formed on the top electrode, wherein the second dielectric layer completely covers the top electrode, and a local interconnect electrode formed on the second dielectric layer.
In another aspect of the present invention, a charge storage capacitor includes a bottom electrode, a first dielectric layer formed on the bottom electrode, a second dielectric layer formed on the first dielectric layer, and a local interconnect electrode formed on the second dielectric layer.
In another aspect of the present invention, a method for forming a capacitor, includes the steps of forming a bottom electrode, forming an encapsulation layer on the bottom electrode, and forming a local interconnect electrode on the encapsulation layer.
In another aspect of the present invention, a method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, includes the steps of forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit, forming a ferroelectric layer on the bottom electrode of the data storage capacitor, forming a top electrode on the ferroelectric layer, forming a first encapsulation layer on the bottom electrode of the charge storage capacitor and a second encapsulation layer on the bottom electrode of the data storage capacitor including the ferroelectric layer and the top electrode, wherein the first encapsulation layer and the second encapsulation are formed simultaneously, and forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer, wherein the first encapsulation layer is a dielectric layer of the charge storage capacitor.
In another aspect of the present invention, a method for forming an integrated circuit comprising a capacitor, includes the steps of forming a bottom electrode, forming a ferroelectric layer on the bottom electrode, forming a top electrode on the ferroelectric layer, forming an encapsulation layer on the top electrode, wherein the encapsulation layer completely covers the top electrode, and forming a local interconnect electrode on the encapsulation layer, wherein the ferroelectric layer includes PZT.
In another aspect of the present invention, a method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, includes the steps of forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit substrate, forming a first ferroelectric layer on the bottom electrode of the charge storage capacitor and a second ferroelectric layer on the bottom electrode of the data storage capacitor, forming a first top electrode on the first ferroelectric layer and a second top electrode on the second ferroelectric layer, forming a first encapsulation layer on the bottom electrode of the charge storage capacitor, including the first ferroelectric layer and the first top layer, forming a second encapsulation layer on the bottom electrode of the data storage capacitor, including the second ferroelectric layer and the second top layer, wherein the first encapsulation layer and the second encapsulation are formed simultaneously, forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer, etching the first interlayer dielectric layer to form a first opening to expose the first encapsulation layer, etching the second interlayer dielectric layer and the second encapsulation layer to form a second opening to expose the top electrode of the data storage capacitor, and forming a first local interconnect electrode in the first opening and a second local interconnect electrode in the second opening, simultaneously, wherein the first local interconnect electrode comprises part of the charge storage capacitor.
In another aspect of the present invention, a method for forming a capacitor, includes the steps of forming a bottom electrode, forming a ferroelectric layer on the bottom electrode, forming an encapsulation layer on the ferroelectric layer, and forming a local interconnect electrode on the encapsulation layer.
In another aspect of the present invention, a method for forming an integrated circuit, comprising a charge storage capacitor and a ferroelectric memory cell including a data storage capacitor, includes the steps of forming a bottom electrode of the charge storage capacitor and a bottom electrode of the data storage capacitor on an integrated circuit substrate, forming a first ferroelectric layer on the bottom electrode of the charge storage capacitor and a second ferroelectric layer on the bottom electrode of the data storage capacitor, forming a top electrode layer on the first and second ferroelectric layers, etching the top electrode layer to remove from the first ferroelectric layer and to form a top electrode of the data storage capacitor on the second ferroelectric layer, forming a first encapsulation layer on the bottom electrode of the charge storage capacitor including the first encapsulation layer and a second encapsulation layer on the bottom electrode of the data storage capacitor including the second ferroelectric layer and the top electrode, and forming a first interlayer dielectric layer on the first encapsulation layer and a second interlayer dielectric layer on the second encapsulation layer, wherein the first encapsulation layer and the second encapsulation are formed simultaneously.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.